Designers of semiconductors, electronic circuits, and printed circuit boards increasingly use design-for-test (DFT) tools when testing products. Older test processes typically involved writing bits in predetermined patterns to test the products. But newer and advanced DFT techniques require faster and more complex protocols to communicate with automated test equipment.
FIG. 1 is a block diagram of automated test equipment in accordance with the prior art. Device-Under-Test (DUT) 100 is connected to several test boards 102, 104, 106. Test boards 102, 104, 106 communicate with workstation 108 via backplane 110. Although only three test boards are shown, automated test equipment can include any number of test boards.
Test boards 102, 104, 106 typically generate stimulus data designed to test DUT 100. Test boards 102, 104, 106 also receive responses from DUT 100. The responses are typically processed by individual test boards 102, 104, 106. When complex test algorithms are required, however, the responses are typically transmitted to workstation 108 for processing and analysis. For example, workstation 108 receives responses when re-calculation of stimulus data or execution of an ancillary or new test procedure is required.
FIG. 2 is a block diagram of a test board for use with automated test equipment according to the prior art. Test board 102 includes memory 200 and test processor 202. Test processor 202 includes stimulus path 204 and response path 206. Stimulus path 204 and response path 206 communicate with DUT 100 (FIG. 1) through pin electronics 208. Although only one memory 200, test processor 202, and pin electronics 208 are shown on test board 102, in practice test board 102 can include any number of these components. For example, a test board can include multiple test processors 202 for testing a single DUT or multiple DUTs.
Stimulus path 204 includes stimulus sequencer 210 and stimulus formatting 212 that transmit test signals to DUT 100. Response path 206 includes response data capture 214 and response and error processing 216 that receive response signals from DUT 100. Workstation 108 transfers data 222 from memory 200 when needed to test DUT 100. The response signals received from DUT 100 are then typically compared with expected response signals to determine the outcome of the test.
As discussed earlier, workstation 108 may generate new data for complex algorithms by reading data from memory 200 and storing new data 222 in memory 200. Controller 218 then obtains the new data from memory 200 and transfers or generates the necessary test data to stimulus path 204. Sending response data to workstation 108, having workstation 108 calculate new data and store the revised data in memory, and then reading the revised data from memory increases the time needed to test DUT 100. And increased test times reduce manufacturing throughput.